CISC 640 Nova Southeastern University
OS Problem Set
Introduction
The following machine description will provide the basis for this assignment. You will
create a virtual machine/operating system for the machine described below that will accept
programs in the target machine language. The details for this assignment are presented
below following the machine description.
MICROPROGRAMMING/MACHINE DISCRIPTION
The following is a description of a machine called SIMMAC that contains the following:
512 32-bit words of memory (memory is word addressable).
Each Instruction consists of a 16-bit opcode and a 16-bit operand.
An ALU for performing mathematical operations.
Registers
ACC Accumulator; A 32-bit register involved in all arithmetic
operations. One of the operands in each arithmetic operation
must be in the Accumulator; the other must be in primary
storage.
PSIAR Primary Storage Instruction Address Register; This 16-bit
register points to the location in primary storage of the next
machine language instruction to be executed.
SAR Storage Address Register; This 16-bit register is involved in all
references to primary storage. It holds the address of the
location in primary storage being read from or written to.
SDR Storage Data Register; This 32-bit register is also involved in
all references to primary storage. It holds the data being
written to or receives the data being read from primary storage
at the location specified in the SAR.
TMPR Temporary Register; This 32-bit register is used to extract the
address portion (rightmost 16-bits) of the machine instruction in
the SDR so that it may be placed in the SAR. (No SDR to SAR
2
transfer.)
CSIAR Control Storage Instruction Address Register; This register
points to the location of the next micro-instruction (in control
storage) to be executed.
IR Instruction Register; This register contains the current
instruction being executed.
MIR Micro-instruction Register; This register contains the current
micro-instruction being executed.
Register Transfers (REG is ACC, PSIAR, or TMPR):
SDR = REG
REG = SDR
SAR = REG
Primary Storage Operations:
READ Data from primary storage location named in the SAR is
placed in the SDR.
WRITE Data in the SDR is placed in primary storage location
named in the SAR.
Sequencing operations:
CSIAR = CSIAR + 1
CSIAR = decoded SDR
CSIAR = constant
SKIP = (add 2 to CSIAR if ACC=0; else add 1)
Operations involving the accumulator:
ACC = ACC + REG
ACC = ACC – REG
ACC = REG
REG = ACC
ACC = REG + 1
Instruction fetch:
3
(00) SAR = PSIAR
(01) READ
(02) IR = SDR
(03) SDR = decoded IR (Operand)
(04) CSIAR = decoded IR (OP CODE)
ADD (Opcode 10):
(10) TMPR = ACC
(11) ACC = PSIAR + 1
(12) PSIAR = ACC
(13) ACC = TMPR
(14) TMPR = SDR
(15) SAR = TMPR
(16) READ
(17) TMPR = SDR
(18) ACC = ACC + TMPR
(19) CSIAR = 0
SUB (Opcode 20):
(20) TMPR = ACC
(21) ACC = PSIAR + 1
(22) PSIAR = ACC
(23) ACC = TMPR
(24) TMPR = SDR
(25) SAR = TMPR
(26) READ
(27) TMPR = SDR
(28) ACC = ACC – TMPR
(29) CSIAR = 0
LOAD (LDA, Opcode 30):
(30) TMPR = ACC
(31) ACC = PSIAR + 1
(32) PSIAR = ACC
(33) ACC = TMPR
(34) TMPR = SDR
(35) SAR = TMPR
(36) READ
(37) ACC = SDR
(38) CSIAR = 0
STORE (Name STR, Opcode 40):
4
(40) TMPR = ACC
(41) ACC = PSIAR + 1
(42) PSIAR = ACC
(43) ACC = TMPR
(44) TMPR = SDR
(45) SAR = TMPR
(46) SDR = ACC
(47) WRITE
(48) CSIAR = 0
BRANCH (Name BRH, Opcode 50):
(50) PSIAR = SDR
(51) CSIAR = 0
COND BRANCH (Name CBR, Opcode 60):
(60) SKIP
(61) CSIAR = 64
(62) PSIAR = SDR
(63) CSIAR = 0
(64) TMPR = ACC
(65) ACC = PSIAR + 1
(65) PSIAR = ACC
(66) ACC = TMPR
(67) CSIAR = 0
LOAD IMMEDIATE (LDI, Opcode 70):
(70) TMPR = ACC
(71) ACC = PSIAR + 1
(72) PSIAR = ACC
(73) ACC = TMPR
(74) ACC = SDR
(75) CSIAR = 0
5
SIMMAC Programming Language Description
Addition
Usage: ADD
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